seiko epson corporation 1 pf468-09 E0C6281 4-bit single chip microcomputer low voltage operation products l core cpu architecture l svd circuit/comparator l melody circuit n description the E0C6281 is an advanced single-chip cmos 4-bit microcomputer consisting of the e0c6200 cmos 4-bit core cpu. it also contains the rom, ram, lcd driver, time base counter and melody generation circuit. the E0C6281 provides an excellent solution for low-power consumption systems with clock functions. n features l cmos lsi ............................................. 4-bit parallel processing l clock ..................................................... 32.768khz (typ.) l instruction set ........................................ 100 instructions l instruction cycle time ............................ 153sec, 214sec or 366sec (depending on instruction) l rom capacity ....................................... 1,024 12 bits l ram capacity ........................................ 96 4 bits l input port ............................................... 5 bits (pull-down resistors are available by mask option) l output port ............................................ 4 bits (general purpose port) 2 bits (for melody output): mo, mo (also used as the external cr connecting terminal for envelope) 1 bit (for lamp output) 1 bit (for clock output: frequency can be selected from 256hz through 32khz by mask option) l i/o port .................................................. 4 bits l lcd driver ............................................. 26 segments 3 commons, 1/3 duty or 4 commons, 1/4 duty l built-in stopwatch timer l built-in supply voltage detection (svd) circuit l built-in comparator ................................ 1 ch. l built-in melody generation circuit .......... equivalent to svm7500 (80-word melody rom is built in) l interrupts ............................................... external : input interrupt 2 lines internal : timer interrupt 1 line stopwatch interrupt 1 line melody completion interrupt 1 line l supply voltage ...................................... 1.5v/3.0v (minimum operating voltage: 0.9v/1.8v) l current consumption ............................ E0C6281/62l81 halt mode : 1.0a (typ.) operating mode : 2.5a (typ.) e0c62a81/62b81 halt mode : 5.5a (typ.) operating mode : 7.2a (typ.) l package ................................................ qfp6-64pin-s1 (plastic) die form n line up model supply voltage 3.0v (1.8v to 3.5v) 1.5v (0.9v to 3.5v) 3.0v (1.8v to 3.5v) 1.5v (0.9v to 3.5v) E0C6281 e0c62l81 e0c62a81 e0c62b81 clock 32khz (crystal oscillation) 32khz (crystal oscillation) 32khz (cr oscillation) 32khz (cr oscillation)
2 E0C6281 n pin configuration qfp6-64pin-s1 < detail of melody function > ? melody memory capacity .................. 80 words ? interval memory capacity .................. 16 words (including one pause note) ? interval generated ............................. c3 to c6 # , or c4 to c7 # (mask option) ? useful note ........................................ 8 (from sixteenth note to a half note) ? tempo ................................................ basic: select 2 tempos out of 16 tempos (30 to 480) (mask option) (the tempo selected is changed by the software control.) the tempo having 8 times, 16 times or 32 times the basic tempo is available by software. ? envelope ............................................ external cr is required. (not available for the piezoelectic direct drive type) ? piezoelectic direct drive .................... envelope not available ? melody control function ..................... (1) 1 music: melody start address is controlled by the software. (2) repeating: the address is controlled by the software when repeated. (3) forcible music change: the new music address is designated with the software while a music is now played. 33 48 17 32 index 16 1 64 49 E0C6281 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 com1 com2 com3 seg25 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 no. pin name 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 seg12 test seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 n.c. p00 no. pin name 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 p01 p02 p03 cmpm cmpp mtest reset k00 k01 k02 k03 k10 r10 r11 r12 mo n.c. = no connection no. pin name 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 r00 r01 r02 r03 v s1 v dd v ss osc2 osc1 v l3 v l2 v l1 cc cb ca com0 no. pin name com0~3 v k00~03, k10 p00~03 r00~03, r10, r11 dd osc1 osc2 reset seg0~25 test v l1~3 ca~cc v s1 v ss power controller lcd driver ram 96 words x 4 bits rom 1,024 words x 12 bits osc system reset control melody interrupt generator input port test port i/o port output port timer stop watch core cpu e0c6200 comparator & svd mo cmpp cmpm r12 mtest n block diagram
3 E0C6281 v dd v ss v s1 v l1 v l2 v l3 ca?c osc1 osc2 k00?03, k10 p00?03 r00?03 r10 r11 r12 mo cmpp cmpm seg0?5 com0? reset test mtest pin name i i o o o o i o i i/o o o o o o i i o o i i i in/out power source (+) terminal power source (-) terminal oscillation and internal logic system regulated voltage output terminal lcd system regulated voltage output terminal (approx. -1.05 v) lcd system booster output terminal (v l1 x 2) lcd system booster output terminal (v l1 x 3) booster capacitor connecting terminal crystal or cr oscillation input terminal crystal or cr oscillation output terminal input terminal i/o terminal output terminal output terminal (fout output available by mask option) output terminal output terminal (melody inverted output and envelope function available by mask option) melody signal output terminal analog comparator non-inverted input terminal analog comparator inverted input terminal lcd segment output terminal (convertible to dc output by mask option) lcd common output terminal initial reset input terminal test input terminal melody test input terminal 54 55 53 60 59 58 61?3 57 56 40?4 32?5 49?2 45 46 47 48 37 36 4?7, 19?0 64, 1? 39 18 38 pin no. function n pin description n electrical characteristics l absolute maximum ratings rating supply voltage input voltage (1) input voltage (2) permissible total output current * 1 operating temperature storage temperature soldering temperature / time permissible dissipation * 2 * 1: * 2: the permissible total output current is the sum total of the current (average current) that simultaneously flows from the outpu t pins (or is draw in). in case of plastic package (qfp6-64pin). symbol v ss v i v iosc s i vss topr tstg tsol p d value -5.0 to 0.5 v ss - 0.3 to 0.5 v ss - 0.3 to 0.5 10 -20 to 70 -65 to 150 260 c, 10sec (lead section) 250 unit v v v ma c c mw (v dd =0v) l recommended operating conditions E0C6281/62a81 condition supply voltage oscillation frequency symbol v ss f osc remark v dd =0v unit v khz (ta=-20 to 70 c) max. -1.8 typ. -3.0 32.768 min. -3.5 e0c62l81/62b81 condition supply voltage oscillation frequency * 1: * 2: when switching to heavy load protection mode. the svd circuit and analog voltage comparator are turned off. the possibility of lcd panel display differs depending on the characteristics of the lcd panel. symbol v ss f osc remark v dd =0v v dd =0v, with software control * 1 v dd =0v, when the analog comparator is used unit v v v khz (ta=-20 to 70 c) max. -1.1 -0.9 * 2 -1.3 typ. -1.5 -1.5 -1.5 32.768 min. -3.5 -3.5 -3.5
4 E0C6281 l dc characteristics E0C6281/62a81 unit v v v v a a a a ma ma ma ma ma ma a a a a a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc =32.768khz, ta=25 c, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. 0 0 0.8? ss 0.90? ss 0.5 16 100 0 -1.0 -1.0 -2.0 -3 -3 -300 typ. min. 0.2? ss 0.10? ss v ss v ss 0 5 30 -0.5 3.0 3.0 4.5 3 3 300 characteristic high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current (1) high level input current (2) high level input current (3) low level input current high level output current (1) high level output current (2) high level output current (3) low level output current (1) low level output current (2) low level output current (3) common output current segment output current (during lcd output) segment output current (during dc output) symbol v ih1 v ih2 v il1 v il2 i ih1 i ih2 i ih3 i il i oh1 i oh2 i oh3 i ol1 i ol2 i ol3 i oh4 i ol4 i oh5 i ol5 i oh6 i ol6 v ih1 =0v no pull down resistor v ih2 =0v with pull down resistor v ih3 =0v with pull down resistor v il =v ss v oh1 =0.1? ss v oh2 =0.1? ss v oh3 =0.1? ss v ol1 =0.9? ss v ol2 =0.9? ss v ol3 =0.9? ss v oh4 =-0.05v v ol4 =v l3 +0.05v v oh5 =-0.05v v ol5 =v l3 +0.05v v oh6 =0.1? ss v ol6 =0.9? ss condition k00?03, k10, p00?03 mtest reset, test k00?03, k10, p00?03 mtest reset, test k00?03, k10, p00?03 cmpp, cmpm k00?03, k10 p00?03 reset, test, mtest k00?03, k10, p00?03 cmpp, cmpm reset, test, mtest r11 r00?03, r10, p00?03 mo, r12 r11 r00?03, r10, p00?03 mo, r12 com0?om3 seg0?eg25 seg0?eg25 e0c62l81/62b81 unit v v v v a a a a a a ma ma a a ma a a a a a a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc =32.768khz, ta=25 c, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. 0 0 0.8? ss 0.90? ss 0.5 10 60 0 -450 -200 -0.8 -0.4 -3 -3 -100 typ. min. 0.2? ss 0.10? ss v ss v ss 0 2.0 9.0 -0.5 1,300 700 1.5 750 3 3 130 characteristic high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current (1) high level input current (2) high level input current (3) low level input current high level output current (1) high level output current (2) high level output current (3) high level output current (4) low level output current (1) low level output current (2) low level output current (3) low level output current (4) common output current segment output current (during lcd output) segment output current (during dc output) symbol v ih1 v ih2 v il1 v il2 i ih1 i ih2 i ih3 i il i oh1 i oh2 i oh3 i oh4 i ol1 i ol2 i ol3 i ol4 i oh5 i ol5 i oh6 i ol6 i oh7 i ol7 v ih1 =0v no pull down resistor v ih2 =0v with pull down resistor v ih3 =0v with pull down resistor v il =v ss v oh1 =0.1? ss v oh2 =0.1? ss v oh3 =0.1? ss v oh4 =0.1? ss when envelope is used v ol1 =0.9? ss v ol2 =0.9? ss v ol3 =0.9? ss v ol4 =0.9? ss when envelope is used v oh5 =-0.05v v ol5 =v l3 +0.05v v oh6 =-0.05v v ol6 =v l3 +0.05v v oh7 =0.1? ss v ol7 =0.9? ss condition k00?03, k10, p00?03 mtest reset, test k00?03, k10, p00?03 mtest reset, test k00?03, k10, p00?03 cmpp, cmpm k00?03, k10 p00?03 reset, test, mtest k00?03, k10, p00?03 cmpp, cmpm reset, test, mtest r11 r00?03, r10, p00?03 mo, r12 mo (r12=normal h level) r11 r00?03, r10, p00?03 mo, r12 mo (r12=normal l level) com0?om3 seg0?eg25 seg0?eg25
5 E0C6281 l analog circuit characteristics and current consumption E0C6281 (normal operating mode) * 1: the svd circuit and analog voltage comparator are turned off. unit v v v v s v mv ms a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. -0.95 2? l1 0.9 3? l1 0.9 -2.25 100 v dd -0.9 10 3 2.5 5.0 typ. -1.05 -2.40 1.0 2.5 min. -1.15 2? l1 -0.1 3? l1 -0.1 -2.55 v ss +0.3 characteristic internal voltage svd voltage svd circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption symbol v l1 v l2 v l3 v svd t svd v ip v im v of t cmp i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) noninverted input (cmpp) inverted input (cmpm) v ip =-1.5v, v im =v ip 15mv during halt during operation * 1 without panel load E0C6281 (heavy load protection mode) * 1: the svd circuit and analog voltage comparator are turned off. unit v v v v s v mv ms a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. -0.95 2? l1 0.85 3? l1 0.85 -2.25 100 v dd -0.9 10 3 5.5 10.0 typ. -1.05 -2.40 2.0 5.5 min. -1.15 2? l1 -0.1 3? l1 -0.1 -2.55 v ss +0.3 characteristic internal voltage svd voltage svd circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption symbol v l1 v l2 v l3 v svd t svd v ip v im v of t cmp i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) noninverted input (cmpp) inverted input (cmpm) v ip =-1.5v, v im =v ip 15mv during halt during operation * 1 without panel load e0c62l81 (normal operating mode) * 1: the svd circuit and analog voltage comparator are turned off. unit v v v v s v mv ms a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. -0.95 2? l1 0.9 3? l1 0.9 -1.10 100 v dd -0.9 20 3 2.5 5.0 typ. -1.05 -1.20 1.0 2.5 min. -1.15 2? l1 -0.1 3? l1 -0.1 -1.30 v ss +0.3 characteristic internal voltage svd voltage svd circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption symbol v l1 v l2 v l3 v svd t svd v ip v im v of t cmp i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) noninverted input (cmpp) inverted input (cmpm) v ip =-1.1v, v im =v ip 30mv during halt during operation * 1 without panel load
6 E0C6281 e0c62l81 (heavy load protection mode) * 1: the svd circuit and analog voltage comparator are turned off. unit v v v v s v mv ms a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. -0.95 2? l1 0.85 3? l1 0.85 -1.10 100 v dd -0.9 20 3 5.5 10.0 typ. -1.05 -1.20 2.0 5.5 min. -1.15 2? l1 -0.1 3? l1 -0.1 -1.30 v ss +0.3 characteristic internal voltage svd voltage svd circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption symbol v l1 v l2 v l3 v svd t svd v ip v im v of t cmp i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) noninverted input (cmpp) inverted input (cmpm) v ip =-1.1v, v im =v ip 30mv during halt during operation * 1 without panel load e0c62a81 (normal operating mode) * 1: the svd circuit and analog voltage comparator are turned off. unit v v v v s v mv ms a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. -0.95 2? l1 0.9 3? l1 0.9 -2.25 100 v dd -0.9 10 3 10.0 12.0 typ. -1.05 -2.40 5.5 7.2 min. -1.15 2? l1 -0.1 3? l1 -0.1 -2.55 v ss +0.3 characteristic internal voltage svd voltage svd circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption symbol v l1 v l2 v l3 v svd t svd v ip v im v of t cmp i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) noninverted input (cmpp) inverted input (cmpm) v ip =-1.5v, v im =v ip 15mv during halt during operation * 1 without panel load e0c62a81 (heavy load protection mode) * 1: the svd circuit and analog voltage comparator are turned off. unit v v v v s v mv ms a a (unless otherwise specified: v dd =0v, v ss =-3.0v, f osc =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. -0.95 2? l1 0.85 3? l1 0.85 -2.25 100 v dd -0.9 10 3 20.0 25.0 typ. -1.05 -2.40 11.0 15.0 min. -1.15 2? l1 -0.1 3? l1 -0.1 -2.55 v ss +0.3 characteristic internal voltage svd voltage svd circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption symbol v l1 v l2 v l3 v svd t svd v ip v im v of t cmp i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) noninverted input (cmpp) inverted input (cmpm) v ip =-1.5v, v im =v ip 15mv during halt during operation * 1 without panel load
7 E0C6281 e0c62b81 (normal operating mode) * 1: the svd circuit and analog voltage comparator are turned off. unit v v v v s v mv ms a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. -0.95 2? l1 0.9 3? l1 0.9 -1.10 100 v dd -0.9 20 3 10.0 12.0 typ. -1.05 -1.20 5.5 7.2 min. -1.15 2? l1 -0.1 3? l1 -0.1 -1.30 v ss +0.3 characteristic internal voltage svd voltage svd circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption symbol v l1 v l2 v l3 v svd t svd v ip v im v of t cmp i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) noninverted input (cmpp) inverted input (cmpm) v ip =-1.1v, v im =v ip 30mv during halt during operation * 1 without panel load e0c62b81 (heavy load protection mode) * 1: the svd circuit and analog voltage comparator are turned off. unit v v v v s v mv ms a a (unless otherwise specified: v dd =0v, v ss =-1.5v, f osc =32.768khz, ta=25 c, c g =25pf, v s1 /v l1 ? l3 are internal voltage , c1?6=0.1 f) max. -0.95 2? l1 0.85 3? l1 0.85 -1.10 100 v dd -0.9 20 3 20.0 25.0 typ. -1.05 -1.20 11.0 15.0 min. -1.15 2? l1 -0.1 3? l1 -0.1 -1.30 v ss +0.3 characteristic internal voltage svd voltage svd circuit response time analog comparator input voltage analog comparator offset voltage analog comparator response time current consumption symbol v l1 v l2 v l3 v svd t svd v ip v im v of t cmp i op condition connect 1m w load resistor between v dd and v l1 (without panel load) connect 1m w load resistor between v dd and v l2 (without panel load) connect 1m w load resistor between v dd and v l3 (without panel load) noninverted input (cmpp) inverted input (cmpm) v ip =-1.1v, v im =v ip 30mv during halt during operation * 1 without panel load
8 E0C6281 l oscillation characteristics the oscillation characteristics change depending on the conditions (components used, board pattern, etc.). use the follow- ing characteristics as reference values. E0C6281 (crystal) unit v v pf ppm ppm ppm v m w (unless otherwise specified: v dd =0v, v ss =-3.0v, crystal: c-002r (c i =35k w ), c g =25pf, c d =built-in, ta=25 c) max. 5 10 -3.5 typ. 20 min. -1.8 -1.8 -10 40 200 characteristic oscillation start voltage oscillation stop voltage built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range harmonic oscillation start voltage permitted leak resistance symbol vsta vstp c d ? f/ ? v ? f/ ? ic ? f/ ? c g v hho r leak condition t sta 3sec t stp 10sec including the parasitic capacity inside the ic v ss =-1.8 to -3.5v c g =5 to 25pf between osc1 and v dd , v ss (v ss ) (v ss ) (v ss ) e0c62l81 (crystal) * 1: items enclosed in parentheses ( ) are those used when operating at heavy load protection mode. unit v v pf ppm ppm ppm v m w (unless otherwise specified: v dd =0v, v ss =-1.5v, crystal: c-002r (c i =35k w ), c g =25pf, c d =built-in, ta=25 c) max. 5 10 -3.5 typ. 20 min. -1.1 -1.1(-0.9) * 1 -10 40 200 characteristic oscillation start voltage oscillation stop voltage built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range harmonic oscillation start voltage permitted leak resistance symbol vsta vstp c d ? f/ ? v ? f/ ? ic ? f/ ? c g v hho r leak condition t sta 3sec t stp 10sec including the parasitic capacity inside the ic v ss =-1.1 to -3.5v (-0.9) * 1 c g =5 to 25pf between osc1 and v dd , v ss (v ss ) (v ss ) (v ss ) e0c62a81 (cr) unit % v ms v (unless otherwise specified: v dd =0v, v ss =-3.0v, r cr =850k w , ta=25 c) max. 20 typ. 32.768khz 3 min. -20 -1.8 -1.8 characteristic oscillation frequency dispersion oscillation start voltage oscillation start time oscillation stop voltage symbol f osc vsta t sta vstp condition v ss =-1.8 to -3.5v (v ss ) (v ss ) e0c62b81 (cr) unit % v ms v (unless otherwise specified: v dd =0v, v ss =-1.5v, r cr =850k w , ta=25 c) max. 20 typ. 32.768khz 3 min. -20 -0.9 -0.9 characteristic oscillation frequency dispersion oscillation start voltage oscillation start time oscillation stop voltage symbol f osc vsta t sta vstp condition v ss =-0.9 to -3.5v (v ss ) (v ss )
9 E0C6281 ca cb cc v v v v osc1 osc2 v reset test mtest vss c1 c2 c3 c4 c5 c6 x'tal l1 l2 l3 dd s1 1.5v or 3.0v piezo buzzer c7 r12 mo k00 k03 k10 p00 p03 cmpp cmpm r00 r03 r10 r11 i i/o o seg0 seg25 com0 com3 lcd panel E0C6281 /62l81 coil r3 c g ca cb cc v v v v osc1 osc2 v reset test mtest vss c1 c2 c3 c4 c5 c6 x'tal l1 l2 l3 dd s1 1.5v or 3.0v piezo buzzer r12 mo k00 k03 k10 p00 p03 cmpp cmpm r00 r03 r10 r11 i i/o o seg0 seg25 com0 com3 lcd panel E0C6281 /62l81 r2 r1 c g n basic external connection diagram note: the above tables are simply an example, and are not guaranteed to work. x'tal c g c1?6 cp r1, r2 crystal oscillator trimmer capacitor capacitor capacitor protection resistor 32.768khz, c i (max.)=35k w 5?5pf 0.1 f 3.3 f 100 w x'tal c g c1?6 c7 cp r3 crystal oscillator trimmer capacitor capacitor capacitor capacitor resistor 32.768khz, c i (max.)=35k w 5?5pf 0.1 f 1 f?0 f 3.3 f 1k w or more
E0C6281 notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is n o representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade control law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 1999 all right reserved. seiko epson corporation electronic devices marketing division ic marketing & engineering group ed international marketing department i (europe & u.s.a.) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5812 fax : 042-587-5564 ed international marketing department ii (asia) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5110 n package dimensions 14 0.1 16.8 0.4 33 48 14 0.1 16.8 0.4 17 32 index 0.35 0.1 16 1 64 49 2.7 0.1 0.1 3.05 max 1.4 0.6 0.15 0 10 0.15 0.05 0.8 plastic qfp6-64pin-s1 unit: mm
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